Yujun Lin

About Me

I am currently a Ph.D. student at MIT HAN Lab of MIT EECS, advised by Prof. Song Han. My research area is the intersection of computer architecture and machine learning, especially software and hardware co-design for deep learning and its applications.

Before coming to MIT, I received my B.Eng. in Electronic Engineering from Tsinghua University. During my undergrad, I was fortunate to work with Professor Bill Dally and Professor Yu Wang.

News

• [02/2025] “QServe: W4A8KV4 Quantization and System Co-design for Efficient LLM Serving” is accepted to MLSys’25.
• [02/2025] “LServe: Efficient Long-Sequence LLM Serving with Unified Sparse Attention” is accepted to MLSys’25.
• [01/2025] “SVDQuant: Absorbing Outliers by Low-Rank Components for 4-Bit Diffusion Models” is accepted to ICLR’25 (Spotlight).
• [01/2025] “SANA: Efficient High-Resolution Image Synthesis with Linear Diffusion Transformers” is accepted to ICLR’25 (Oral).
• [10/2024] “LEGO: Spatial Accelerator Generation and Optimization for Tensor Applications” is accepted to HPCA’25.
• [05/2023] “VideoTime³: A 40-uJ/frame 38 FPS Video Understanding Accelerator With Real-Time DiffFrame Temporal Redundancy Reduction and Temporal Modeling” is accepted to IEEE Solid-State Circuits Letters.
• [08/2022] “TorchSparse: Efficient Point Cloud Inference Engine” is accepted to MLSys’22.
• [04/2022] “QuantumNAS: Noise-Adaptive Search for Robust Quantum Circuits” is accepted to HPCA’22.
• [10/2021] Seleted as DAC Young Fellow 2021.
• [07/2021] “PointAcc: Efficient Point Cloud Accelerator” is accepted to MICRO’21.
• [06/2021] Got into the 2021 Qualcomm Innovation Fellowship winners list
• [02/2021] “NAAS: Neural Accelerator Architecture Search” is accepted to DAC’21.

Selected Publications

Services

• Conference Reviewer: ICLR, ICML, NeurIPS
• Journal Reviewer: TPAMI, TACD, TCSVT, TETC, TKDE, TNNLS, VISI

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